For data recovery with a relatively low bit-error rate (BER), it is desirable to sample the data-carrying analog signal at proper times (sampling phases) for having it quantized and digitized in an analog-to-digital converter (ADC). To increase the data rate, a multi-channel ADC architecture may be used in which the individual channel ADCs operate at a relatively low speed while the effective higher speed is achieved by time-interleaving their outputs. However, one problem with the multi-channel ADC architecture is that the sampling phases of the individual channel ADCs may be misaligned, e.g., due to fabrication-process variances affecting different channel ADCs in different ways, temperature variations, and circuit aging. Disadvantageously, the misalignment of sampling phases may generate undesirable noise and degrade the overall performance characteristics of a time-interleaved ADC.